The present invention relates to a fault analyzing apparatus using an electron beam tester for testing a change in voltage of a semiconductor integrated circuit and a method therefor.
When voltage waveform information acquired using an electron beam tester is to be used for analyzing and localizing a fault origin of a semiconductor integrated circuit (to be referred to as a DUT (Device Under Test) hereinafter), the assistance of a designer or design information (to be referred to as CAD data hereinafter) such as CAD (Computer Aided Design) database is disadvantageously required, or the voltage waveform information disadvantageously cannot be used until a fault origin is localized to some extent by another method. At a site at which a fault analysis is to be performed, a designer is not always present, and CAD data cannot always be obtained. In this case, a method of comparing voltage contrast images with each other is proposed as an effective localizing method. This method is called a dynamic fault imaging method (to be referred to as a DFI method) (the first prior art). For example, the method is described as T. C. May et al., "Dynamic Fault Imaging of VLSI Random Logic Devices", 1984 IEEE/IRPS, pp. 95 to 108.
The timing charts of the DFI method are shown in FIGS. 6A to 6C. As shown in FIG. 6A, a test vector is constituted by the repetition of test patterns 1 to 4 from which an image is to be acquired. The test patterns 1 to 4 represent signals for testing a DUT for each clock in FIG. 6B. Only when one specific test pattern is supplied, for example, as shown in FIG. 6C, an electron beam is irradiated as a pulse for 200 ps to 5 .mu.s during only the test pattern 4 period (stroboscopic method). In this manner, this method has the following characteristic feature. That is, while the DUT is driven, the voltage contrast images of the test patterns with respect to faulty and faulty-free integrated circuits are acquired. Portions (faulty images) which are obtained by the difference between the voltage contrast images and which are different from each other in brightness are traced while the test patterns are referred to, thereby localizing a fault origin. However, when the DFI is to be applied, due to the limitation of the sizes (scanning range and magnification) of an electronic optical system, an increase in DUT area, and an increase in wiring density, the voltage contrast images of the entire surface of the DUT cannot be obtained at once at a resolving power which is sufficient to observe the voltages of elements of wiring lines. As a DUT increases in scale, the number of series of test patterns for testing the DUT increases. For this reason, a signal-to-noise ratio of a voltage contrast image decreases, thereby disadvantageously requiring a long time for acquiring an image.
In "Development of rapid voltage contrast image acquisition technique and its application to LSI fault origin localization" (Nakamura, et al., 1992, IEICE technical researching report of the study of Reliability of IEICE, pp. 43 to 48, R91-68 CPM91-1135), Nakamura et al., in order to solve the problem of prolonging a time for acquiring an image, are successful in shortening the time for acquiring the image as a whole on the basis of increase the ratio of a time for acquiring an image signal to the unit time by prolonging the time for inputting, to a DUT, a test pattern designed to acquire the image. This method is called a CGFI method (Continuous e-beam with synchronized Gated signal acquisition Fault Imaging technique), and has a characteristic feature in which a continuous beam is used as an incident electron beam.
The timing charts of the CGFI method are shown in FIGS. 8A to 8D. As shown in FIG. 8C, secondary electrons are continuously generated by applying a continuous electron beam. However, only when a test pattern from which a voltage contrast image is acquired is supplied by the gate pulse shown in FIG. 8D, e.g., only when the test pattern 4 of the test vector shown in FIG. 8A is supplied, a supply time is prolonged by 50 .mu.s to 1 s, and data obtained during the supply time is received by an image processor to form a voltage contrast image. FIG. 8B shows a clock for switching test patterns.
The arrangement of an apparatus for performing the above CGFI method is shown in FIG. 7. Referring to FIG. 7, reference numeral 101 denotes a program memory for storing a control program for performing an LSI test; 102, a data memory for storing test pattern data constituting a test vector; 103, a computer for executing an LSI test in accordance with the control program stored in the program memory 101; 104, an LSI tester; 105, an electron beam tester; 106, a signal line for supplying the test pattern data stored in the data memory 102 to the electron beam tester 105; 107, an image acquiring timing line for transmitting a gate pulse from the LSI tester 104 to the electron beam tester 105; 108, a DUT serving as a target to be tested; 109, an electron beam irradiated on the DUT 108; 110, a secondary electron detector for detecting secondary electrons 115 from the DUT 108; 111, a gate circuit for extracting voltage contrast image data from the secondary electron detector 110 on the basis of the gate pulse of the image timing signal line 107; 112, a computer for receiving the voltage distribution data extracted by the gate circuit 111; 113, an image processor 113 for imaging the voltage contrast image data received by the computer 112; 114, a GPIB (General Purpose Interface Bus) control line for transmitting and receiving a control signal between the computers 103 and 112; 116, a CRT monitor for displaying the voltage contrast image imaged by the image processor 113; 117, an electron gun assembly for generating the electron beam 109; 118, a socket to which the DUT 108 is connected; and 119, a connector of the LSI tester 104.
Nakamura et al., connect the electron beam tester 105 to the LSI tester 104 through the GPIB control line 114 such that a test pattern changing operation performed when these test patterns are referred to, i.e., when an editing operation of the test patterns (change operation of a test pattern to be designated, a setting operation of prolongation of an input time, or a setting operation of a test pattern performed to prevent the test pattern following the designated test pattern from being input to the DUT 108) is automatically performed. In this manner, by using a voltage contrast image formed on the basis of the detection amount of the secondary electrons 115 obtained by irradiating the electron beam 109 from the electron gun assembly 117 onto the DUT 108, in a system for specifying a faulty circuit portion of the DUT 108, as described in FIGS. 8A to 8D, Nakamura et al., acquire a voltage contrast image such that a time for inputting, to an integrated circuit, a test pattern, of a series of test patterns repeatedly input to the integrated circuit, designated to acquire a voltage contrast image is set to be longer than a time for inputting each of the remaining test patterns, thereby acquiring an image at a high speed (the second prior art).
However, in the second prior art, when an electron beam is to be irradiated on an LSI chip with an insulating film, the levels of test patterns may be deviated to high or low, or a voltage contrast may decrease due to the influence of a charge-up phenomenon when a fixed voltage fault occurs. Therefore, a voltage level cannot easily be determined from a voltage image.